• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention stores the digital image data output from the analog / digital conversion unit in the frame memory by one frame amount, and reads the image data stored in the frame memory by one line amount and provides the image data to the address driving IC (Integrated Circuit) unit. The present invention relates to a data processing circuit of Plasma Display Panel-TeleVision (PDP-TV). The present invention comprises a first and second PISO unit, a data recording unit, a first data reading unit, a first and second data storage unit, and a second data reading unit and outputting image data from an analog / digital converter. Is classified by bit weight into a frame memory in a predetermined order, and the image data is read out from the frame memory in a line order and supplied according to the data format required by the address driver IC unit. There is an effect that the signal can be efficiently displayed on the PDP driven by the sequential scanning method.
    公开号:KR20000021545A
    申请号:KR1019980040696
    申请日:1998-09-30
    公开日:2000-04-25
    发明作者:김세용
    申请人:전주범；대우전자 주식회사；
    IPC主号:
    专利说明:

    Data processing unit of a PDP television
    BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to PDP-TV (PDP-TV: Plasma Display Panel-TeleVision). In particular, the digital image data output from the analog / digital converter is stored in the frame memory by one frame amount, and the image data is stored in the frame memory. The present invention relates to a data processing circuit of a PDP-TV which reads a line by one line and provides it to an address driver IC (Integrated Circuit) unit.
    In general, a PDP is a flat panel display panel using a penning gas for discharge, i.e., gases based on Ne or Helium gas having a relatively high atmospheric pressure (over 100 Torr) are coated with a dielectric. The panel which uses the light emission phenomenon obtained by discharging between narrow electrodes.
    The penning gas is mainly Ne + Xe, Ne + He + Xe, and the reason for using such a mixed gas is that the discharge start voltage can be lowered when the mixed gas is more than one gas component. The discharge start voltage depends on the type of gas, the fanning gas pressure, and the structure and shape of the panel.
    The PDP has the following advantages over other display devices.
    First of all, the PDP is not limited to the number of horizontal and vertical display lines, so that a large size can be manufactured and multiplexing techniques can be used to reduce the number of driving circuits.
    Since the discharging material is a gas, the refractive index value is 1, which means that the light is not extinguished by the internal reflection and the external light is not reflected or scattered by the display material. In addition, unlike other flat panels, the PDP is sealed with glass above 400 ° C, which means that the PDP can operate even under high humidity conditions or the presence of reactive gases. It is only a change.
    The PDPs are classified into AC type PDPs and DC type PDPs according to the type of driving voltage applied to the discharge cells. The AC type PDP is driven by a sine wave AC voltage or a pulse voltage, while the DC type PDP is driven by a DC voltage. In addition, in the AC type PDP, the electrode is covered with a dielectric of glass, whereas in the DC type PDP, the electrode is exposed as it is and a discharge current flows while the discharge voltage is applied.
    In general, a PDP-TV can display a TV image on the PDP only by converting an interlaced scanning analog NTSC composite video signal into a sequential scanning digital image data due to the display characteristics of the PDP.
    In addition, the PDP-TV divides and drives one field screen into a plurality of subfield screens to realize gray scale of an image. To this end, the PDP-TV drives one frame of image data with the most significant bit (MSB). Reorder from Most Significant Bit (LSB) to Least Significant Bit (LSB).
    In order to convert the image data as described above, the PDP-TV includes an analog / digital converter for digitizing an analog video signal, a frame memory for storing one frame of image data output from the analog / digital converter, and the frame memory. And an address driver IC unit for receiving the image data stored in the driver and driving the address electrode line of the PDP.
    The image data output from the analog / digital converter is to be stored in the frame memory by one frame, and the image data stored in the frame memory is read by one line and supplied according to the data type required by the address driver IC. In the related art, there is a problem in that an NTSC composite video signal cannot be accurately displayed on a PDP because a specific circuit for performing such data processing is not implemented.
    The present invention has been made to solve the above problems, and stores the image data output from the analog / digital conversion unit in the frame memory by one frame, and reads the image data stored in the frame memory by one line It is an object of the present invention to provide a data processing circuit of a PDP-TV which is supplied in accordance with the data format required by the address driver IC unit.
    In order to achieve the above object, the data processing circuit of the PDP-TV according to the present invention includes an analog / digital converting unit for digitizing an analog image signal and the image data output from the analog / digital converting unit by 1 frame amount, respectively. In a PDP-TV having two frame memories for storing and an address driver IC for receiving the image data stored in the frame memory and driving the address electrode lines of the PDP, the image data output from the analog / digital converter is The first and second PISO units alternately repeating the load operation and the shift operation so as to be classified by bit weight, and the same output from the PISO unit shifted among the first PISO unit and the second PISO unit. Data device for recording bit-weighted image data in order in one of the two frame memories. And a first data reading section for reading line-by-line video data already stored in the remaining one frame memory in which no data is recorded by the data recording section, and video data read by the data reading section. First and second data storage units for alternately storing each of the first and second data storage units, and one line of image data stored in the first or second data storage units according to the data type required by the address driver IC unit. And a second data reading unit.
    1 is a schematic configuration diagram of a PD TV to which the present invention is applied;
    FIG. 2 is a schematic configuration diagram of a data processor and a memory unit illustrated in FIG. 1.
    <Description of the symbols for the main parts of the drawings>
    120: analog / digital conversion unit 130: data processing unit
    130-1: First PISO Part 130-2: Second PISO Part
    130-3: data recording unit 130-4: first data reading unit
    130-5: first data storage unit 130-6: second data storage unit
    130-7: second data reader 140: memory
    140-1: First Frame Memory 140-2: Second Frame Memory
    200: PDDP
    Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
    1 is a schematic configuration diagram of a PDP-TV to which the present invention is applied, and the audio / video unit 110 receives an NTSC composite video signal through an antenna and outputs analog R (Red), G (Green), and B (Blue). The signal is separated from the horizontal and vertical sync signals (Hsync, Vsync), and an APL (Average Picture Level) corresponding to the average value of the luminance signal is obtained and provided to the analog / digital converter 120. Here, the NTSC composite video signal has an interlaced scanning method in which one frame consists of two fields, odd and even, a horizontal sync signal (Hsync) has a frequency of about 15.73KHz, and a vertical sync signal (Vsync) has a frequency of about 60Hz. .
    The analog / digital converter 120 converts the analog R, G, and B signals received from the audio / video unit 110 into N-bit digital image data, respectively, and provides them to the data processor 130. In this case, when the analog image signal is converted into N-bit digital image data, 2N gray scale is implemented. For example, when converting an analog video signal into 8-bit digital video data, 2 8 = 256 gray levels are implemented.
    The data processor 130 rearranges the digital R, G, and B data received from the analog / digital converter 120 by the bit weights from the most significant bit (MSB) to the least significant bit (LSB) to the memory unit 140. The upper and lower address driver ICs are stored in the memory unit 140, and the image data stored in the memory unit 140 is read out by one line for the data type required by the upper and lower address driver IC units 150-1 and 150-2. It supplies to the parts 150-1 and 150-2.
    As shown in FIG. 2, the memory unit 140 stores first and second frame memories 140-1 and 140 for R (Red), G (Green), and B (Blue) data, respectively, by one frame. It consists of -2). For example, when 2 8 = 256 gray levels are implemented in a PDP having a resolution of 853 × 480, the first or second frame memories 140-1 and 140-2 may have one frame, that is, 853 × 3 (R, G, B) × 480 × 8 bits = It should be able to store about 10Mbit of image data. In this case, the two frame memories 140-1 and 140-2 are provided to simultaneously record and read image data by the data processor 130. That is, while one of the two frame memories 140-1 and 140-2 is operated in the image data recording mode, the other is operated in the image data reading mode.
    The upper address driver IC unit 150-1 shown in FIG. 1 is an odd-numbered address electrode line of the PDP 200 according to "high" and "low" of R, G, and B data supplied from the data processor 130. The address pulses are applied to the respective address pulses, and the lower address driving IC unit 150-2 is even-numbered of the PDP 200 according to the "high" and "low" of the R, G, and B data supplied from the data processing unit 130. An address pulse is applied to each of the address electrode lines.
    The scan and sustain driving IC unit 160 shown in FIG. 1 applies scan pulses and sustain pulses to the scan and sustain electrode lines of the PDP 200, respectively, and the timing controller 170 controls the audio / video unit 110. Receives the horizontal and vertical synchronization signals Hsync and Vsync output to generate a data read clock (data read CLK) and supply them to the data processor 130, and generate various logic control pulses to supply the high voltage driving circuit unit 180. do.
    The high voltage driving circuit unit 180 combines the DC voltages supplied from the AC-DC converter 190 according to various logic control pulses output from the timing controller 170 to upper and lower address driving IC units 150-1. 150-2) and the high voltage control pulse required by the scan and sustain driver IC unit 160 to drive the PDP 200. In addition, the data streams supplied by the data processing unit 130 to the upper and lower address driving IC units 150-1 and 150-2 are also raised to an appropriate voltage level to enable selective writing to the PDP 200.
    The AC-DC converter 190 generates AC voltages (220V AC, 60Hz) as inputs to generate high voltages required to combine the electrode driving pulses and all DC voltages required by each component constituting the system. Supply.
    FIG. 2 is a schematic configuration diagram of the data processing unit and the memory unit illustrated in FIG. 1, wherein the data processing unit 130 includes first and second PISO units 130-1 and 130-2, and a data recording unit 130-3. ), A first data reader 130-4, first and second data storage units 130-5 and 130-6, and a second data reader 130-7. The memory unit 140 includes first and second frame memories 140-1 and 140-2.
    The first and second PISO units 130-1 and 130-2 perform a load operation and shift so that R, G, and B data output from the analog / digital converter 120 shown in FIG. 1 are classified by bit weights. Repeat the action alternately. In addition, the first and second PISO units 130-1 and 130-2 each include an R PISO (not shown) for loading or shifting R data, and a G PISO (not shown) for loading or shifting G data. Not shown) and B PISO (not shown) for loading or shifting B data.
    In the above, the two PISO units 130-1 and 130-2 are provided while one of the first and second PISO units 130-1 and 130-2 loads the image data while the other one is previously loaded. This is for shifting and outputting the image data for each bit weight, that is, for simultaneously loading and shifting the image data.
    The data recording unit 130-3 may output image data having the same bit weight from the first PISO unit 130-1 and the second PISO unit 130-2 by the shifted PISO unit in the first or second frame. The memories are written to the memory 140-1 and 140-2 in order.
    The first data reading unit 130-4 stores one line of video data already stored in one frame memory in which data is not recorded by the data recording unit 130-3 with a period of one horizontal line display period. Read it bit by bit.
    The first and second data storage units 130-5 and 130-6 alternately store R, G, and B data read by the data reading unit 130-4 by one line. For example, when 2 8 = 256 gray scales are implemented in a PDP having a resolution of 853 × 480, the first or second data storage units 130-5 and 130-6 have one line, that is, 853 × 3 (R, G, B) = It should be able to store 2559 bits of image data.
    The two data storage units 130-5 and 130-6 are also provided to simultaneously record and read image data. That is, while one line of image data is recorded in one of the two data storage units 130-5 and 130-6, one line of image data already stored is read in the other.
    The second data reading unit 130-7 shown in FIG. 2 is configured to display one line of image data stored in the first or second data storage units 130-5 and 130-6 as shown in FIG. 1. Supply is performed in accordance with the data format required by the address driver IC units 150-1 and 150-2.
    Referring to the operation of the data processing unit 130 configured as described above in more detail as follows.
    In the following description, an example of implementing 2 8 = 256 gray scales in the PDP 200 having a resolution of 853 × 480 will be described as an example.
    First, when the resolution of the PDP 200 is 853 × 480 and 256 gray levels are implemented, the analog / digital converter 120 has 3 (R, G, B) × 8 (bits) = 24 in the R / G and B data. Bit by bit are output in parallel.
    In the above state, R PISO, G PISO, and B PISO of the first PISO unit 130-1 total 8 × 16 of 8 times of image data output from the analog / digital converter 120 in 16 times, respectively. = 128 bits After loading, output is sequentially shifted eight times, 16 bits from most significant bit (MSB) to least significant bit (LSB). At this time, the R PISO, G PISO, and B PISO of the second PISO unit 130-2 shift and output the previously loaded image data when the image data of the first PISO unit 130-1 is loaded. 1 When the image data is shifted by the PISO unit 130-2, the image data output from the analog / digital converter 120 is loaded.
    On the other hand, the R, G, B image data output in parallel by 16x3 (R, G, B) = 48 bits in the first or second PISO unit (130-1, 130-2) is the data recording unit 130 -3) is sequentially written to the first or second frame memories 140-1 and 140-2. The video data recording operation is repeated until one frame of video data is recorded in the frame memory.
    At the same time, the first data reading unit 130-4 is one line from the frame memory in which the image data is not recorded by the data recording unit 130-3 of the two frame memories 140-1 and 140-2. The R, G, and B data are read and output to the first or second data storage units 130-5 and 130-6. Here, the first data reading unit 130-4 reads one line of image data 54 times in 48 bits (more specifically, only 15 bits in the last 54 times can read a total of 2559 bits). ) Outputs to the first or second data storage unit 130-5 and 130-6. In addition, the first data reading unit 130-4 may alternately store one line of image data in the first and second data storage units 130-5 and 130-6 with one horizontal line display period. do.
    One line of image data stored in the first or second data storage units 130-5 and 130-6 corresponds to a data type required by the upper and lower address driving IC units 150-1 and 150-2. The data is read by the second data reading unit 130-7 over 32 times and supplied to the upper and lower address driving IC units 150-1 and 150-2.
    As described above, according to the present invention, the image data output from the analog / digital converter is classified by bit weights and recorded in a predetermined order in the frame memory by one frame amount, and the image driver is read out by one line amount from the frame memory. By supplying the data according to the data type required by the interfering scanning method, an analog image signal of the interlaced scanning method can be efficiently displayed on the PDP driven by the progressive scanning method.
    权利要求:
    Claims (1)
    [1" claim-type="Currently amended] An analog / digital converter for digitizing an analog video signal, two frame memories for storing one frame of image data output from the analog / digital converter, and image data stored in the frame memory to receive the PDP. In a PDP-TV having an address driver IC unit for driving an address electrode line,
    First and second PISO units which alternately repeat the load operation and the shift operation so that the image data output from the analog / digital converter is classified by bit weights;
    A data recording unit for sequentially recording image data having the same bit weight output from the PISO unit shifted among the first PISO unit and the second PISO unit into one of the two frame memories;
    A first data reading section which reads, by a line amount, video data already stored in the remaining one frame memory in which no data is recorded by the data recording section;
    First and second data storage units for alternately storing image data read by the data reading unit by one line;
    And a second data reading unit for supplying one line of image data stored in the first or second data storage unit in accordance with the data format required by the address driving IC unit.
    类似技术:
    公开号 | 公开日 | 专利标题
    US5436634A|1995-07-25|Plasma display panel device and method of driving the same
    US5818419A|1998-10-06|Display device and method for driving the same
    US6323880B1|2001-11-27|Gray scale expression method and gray scale display device
    US6646629B2|2003-11-11|Liquid crystal display control device, liquid crystal display device using the same, and information processor
    ES2274776T3|2007-06-01|Method for controlling the power level of a presentation device and appliance to carry out that method.
    KR100450179B1|2004-09-24|Driving method for plasma display panel
    US7015648B2|2006-03-21|Plasma display panel driving method and apparatus capable of realizing reset stabilization
    KR100420022B1|2004-02-25|Driving method for plasma display panel using variable address voltage
    US6646625B1|2003-11-11|Method for driving a plasma display panel
    JP3556138B2|2004-08-18|Display device
    US7365767B2|2008-04-29|Apparatus for driving plasma display panel and method for displaying pictures on plasma display panel
    US6608610B2|2003-08-19|Plasma display device drive identifies signal format of the input video signal to select previously determined control information to drive the display
    KR100660579B1|2006-12-22|Plasma display apparatus
    US6825835B2|2004-11-30|Display device
    US7173578B2|2007-02-06|Method and apparatus for driving a plasma display panel in which reset discharge is selectively performed
    US7477215B2|2009-01-13|Plasma display apparatus and driving method thereof
    US6331862B1|2001-12-18|Image expansion display and driver
    US6222511B1|2001-04-24|AC plasma gas discharge gray scale graphics, including color, and video display drive system
    KR100446935B1|2004-09-08|Display image displaying method
    KR100445731B1|2004-11-06|The driving circuit of the display device
    JP4010983B2|2007-11-21|Plasma display panel address data automatic power control method and apparatus, and plasma display panel apparatus having the apparatus
    KR100799746B1|2008-02-01|Method and apparatus for processing video pictures for display on a display device
    KR100924105B1|2009-10-29|Method and apparatus for processing video pictures
    JP3580027B2|2004-10-20|Plasma display device
    US6236380B1|2001-05-22|Method for displaying gradation with plasma display panel
    同族专利:
    公开号 | 公开日
    KR100403514B1|2003-12-18|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1998-09-30|Application filed by 전주범, 대우전자 주식회사
    1998-09-30|Priority to KR10-1998-0040696A
    2000-04-25|Publication of KR20000021545A
    2003-12-18|Application granted
    2003-12-18|Publication of KR100403514B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR10-1998-0040696A|KR100403514B1|1998-09-30|1998-09-30|PDTV's data processing circuit|
    [返回顶部]